View 48LC16M16A2_1564870.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

products and specifications discussed herein ar e subject to change by micron without notice. 256mb: x4, x8, x16 sdram features pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_1.fm - rev. l 10/07 en 1 ?1999 micron technology, inc. all rights reserved. synchronous dram mt48lc64m4a2 ? 16 meg x 4 x 4 banks mt48lc32m8a2 ? 8 meg x 8 x 4 banks mt48LC16M16A2 ? 4 meg x 16 x 4 banks for the latest data sheet, refer to micron?s web site: www.micron.com features ? pc100- and pc133-compliant ? fully synchronous; all signals registered on positive edge of system clock ? internal pipelined operatio n; column address can be changed every clock cycle ? internal banks for hiding row access/precharge ? programmable burst lengths: 1, 2, 4, 8, or full page ? auto precharge, includes co ncurrent auto precharge, and auto refresh modes ? self refresh mode ? 64ms, 8,192-cycle refresh ? lvttl-compatible inputs and outputs ? single +3.3v 0.3v power supply part number example: mt48LC16M16A2tg-75:d table 1: address table parameter 64 meg x 4 32 meg x 8 16 meg x 16 configuration 16 meg x 4 x 4 banks 8 meg x 8 x 4 banks 4 meg x 16 x 4 banks refresh count 8k 8k 8k row addressing 8k (a0?a12) 8k (a0?a12) 8k (a0?a12) bank addressing 4 (ba0, ba1) 4 (ba0, ba1) 4 (ba0, ba1) column addressing 2k (a0?a9, a11) 1k (a0?a9) 512 (a0?a8) table 2: key timing parameters cl = cas (read) latency speed grade clock frequency access time setup time hold time cl = 2 cl = 3 -6a 167 mhz ? 5.4ns 1.5ns 0.8ns -7e 143 mhz ? 5.4ns 1.5ns 0.8ns -75 133 mhz ? 5.4ns 1.5ns 0.8ns -7e 133 mhz 5.4ns ? 1.5ns 0.8ns -75 100 mhz 6ns ? 1.5ns 0.8ns notes: 1. refer to micron technical note: tn-48-05 . 2. off-center parting line. 3. contact micron for availability. options marking ? configurations ? 64 meg x 4 (16 meg x 4 x 4 banks) ? 32 meg x 8 (8 meg x 8 x 4 banks) ? 16 meg x 16 (4 meg x 16 x 4 banks) 64m4 32m8 16m16 ?write recovery ( t wr) ? t wr = ?2 clk? 1 a2 ?plastic package ? ocpl 2 ? 54-pin tsop ii ocpl 2 (400 mil) (standard) ? 54-pin tsop ii ocpl 2 (400 mil) pb-free ? 60-ball fbga (x4, x8) (8mm x 16mm) ? 60-ball fbga (x4, x8) pb-free (8mm x 16mm) ? 54-ball vfbga (x16) (8mm x 14 mm) ? 54-ball vfbga (x16) pb-free (8mm x 14 mm) tg p fb bb fg bg ? timing (cycle time) ? 6.0ns @ cl = 3 (x8, x16 only) ? 7.5ns @ cl = 3 (pc133) ? 7.5ns @ cl = 2 (pc133) -6a -75 -7e ? self refresh ? standard ? low power none l 3 ? operating temperature range ? commercial (0c to +70c) ? industrial (?40c to +85c) none it ?design revision :d
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdramtoc.fm - rev. l 10/07 en 2 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 pin/ball assignments and descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 mode register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 burst length (bl). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 operating mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 write burst mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 cas latency (cl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 the command inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 no operation (nop). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 load mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 burst terminate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 auto refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 bank/row activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 clock suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 burst read/single write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 concurrent auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 read with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 write with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 temperature and thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdramlof.fm - rev. l 10/07 en 3 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram list of figures list of figures figure 1: 64 meg x 4 sdram function al block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 2: 32 meg x 8 sdram function al block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 3: 16 meg x 16 sdram functional bloc k diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 4: 54-pin tsop assignment (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 5: 60-ball fbga assignment (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 6: 54-ball fbga assignment (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 7: mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 8: cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 9: terminating a write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 10: activating a specific row in a specific bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 11: example: meeting t rcd (min) when 2 < t rcd (min)/ t ck 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 12: read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 13: consecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 14: random read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 15: read-to-write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 16: read-to-write with extra clock cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 17: read-to-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 18: terminating a read bu rst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 19: write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 20: write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 21: write-to-write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 22: random write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 23: write-to-read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 24: write-to-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 25: precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 26: power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 27: clock suspend during write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 28: clock suspend during read burs t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 29: read with auto precharge interrupted by a read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 30: read with auto precharge interr upted by a write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 31: write with auto precharge interrupted by a read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 32: write with auto precharge interrupted by a write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 33: example temperature test point location, 54-pin tsop : top view . . . . . . . . . . . . . . . . . . . . . . . . . . .4 8 figure 34: example temperature test point location, 54-ball vfbg a: top view . . . . . . . . . . . . . . . . . . . . . . . . .48 figure 35: example temperature test point location, 60-ball fbga : top view . . . . . . . . . . . . . . . . . . . . . . . . . .4 8 figure 36: initialize and load mode regist er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 37: power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 38: clock suspend mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 figure 39: auto refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 figure 40: self refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 figure 41: read ? without auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 figure 42: read ? with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 figure 43: single read ? without auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 figure 44: single read ? with auto precha rge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 figure 45: alternating bank read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 figure 46: read ? full-page burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 figure 47: read ? dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 figure 48: write ? without auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 figure 49: write ? with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 figure 50: single write ? without auto prec harge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 figure 51: single write ? with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 figure 52: alternating bank writ e accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 figure 53: write ? full-page burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 figure 54: write ? dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 figure 55: 54-pin plastic tsop (4 00 mil) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 figure 56: 60-ball fbga ?fb? package, 8mm x 16mm (x4, x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdramlof.fm - rev. l 10/07 en 4 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram list of figures figure 57: 54-ball vfbga ?fg? package, 8mm x 14mm (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdramlot.fm - rev. l 10/07 en 5 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram list of tables list of tables table 1: address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: key timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 3: 256mb sdram part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 table 4: 54-pin tsop descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 5: 54-ball and 60-ball fbga descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 6: burst definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 7: cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 8: truth table 1 ? commands and dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 9: truth table 2 ? cke . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 10: truth table 3 ? current state bank n, command to bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 11: truth table 4 ? current state bank n, command to bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 12: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 13: temperature limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 14: thermal impedance simulated values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 15: dc electrical characteristics and operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 16: i dd specifications and conditions (-6a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 17: i dd specifications and conditions (-7e, -75) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 18: capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 table 19: electrical characteristics and re commended ac operating conditions (-6a) . . . . . . . . . . . . . . . . . .51 table 20: electrical characteristics and recommended ac operating conditions (-7e, -75) . . . . . . . . . . . . . .52 table 21: ac functional characteristics (-6a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 table 22: ac functional characteristics (-7e, -75) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 6 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram general description notes: 1. actual fbga part marking shown on pages 76 and 77. general description the 256mb sdram is a high-speed cmos, dy namic random-access memory containing 268,435,456 bits. it is internally configured as a quad-bank dram with a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). each of the x4?s 67,108,864-bit banks is organized as 8,192 rows by 2,048 columns by 4 bits. each of the x8?s 67,108,864-bit banks is organized as 8,192 rows by 1,024 columns by 8 bits. each of the x16?s 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits. read and write accesses to the sdram are bu rst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0, ba1 select the bank; a0?a12 select the row). the address bits registered coincident with the read or write command are used to select the star ting column location for the burst access. the sdram provides for programmable read or write burst lengths (bl) of 1, 2, 4, or 8 locations, or the full page, with a burst te rminate option. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. the 256mb sdram uses an internal pipelined architecture to achieve high-speed opera- tion. this architecture is compatible with the 2 n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. precharging one bank wh ile accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. the 256mb sdram is designed to operate in 3.3v memory systems. an auto refresh mode is provided, along with a power-saving , power-down mode. all inputs and outputs are lvttl-compatible. table 3: 256mb sdram part numbers part numbers architecture package mt48lc64m4a2tg 64 meg x 4 54-pin tsop ii mt48lc64m4a2p 64 meg x 4 54-pin tsop ii mt48lc64m4a2fb 1 64 meg x 4 60-ball fbga mt48lc64m4a2bb 1 64 meg x 4 60-ball fbga mt48lc32m8a2tg 32 meg x 8 54-pin tsop ii mt48lc32m8a2p 32 meg x 8 54-pin tsop ii mt48lc32m8a2fb 1 32 meg x 8 60-ball fbga mt48lc32m8a2bb 1 32 meg x 8 60-ball fbga mt48LC16M16A2tg 16 meg x 16 54-pin tsop ii mt48LC16M16A2p 16 meg x 16 54-pin tsop ii mt48LC16M16A2fg 16 meg x 16 54-ball fbga mt48LC16M16A2bg 16 meg x 16 54-ball fbga
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 7 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram general description sdrams offer substantial advances in dr am operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to inte rleave between internal banks to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. figure 1: 64 meg x 4 sdram functional block diagram 13 ras# cas# row- address mux clk cs# we# cke control logic column- address counter/ latch mode register 11 command decode a0?a12, ba0, ba1 dqm 13 address register 15 2,048 (x4) 8,192 i/o gating dqm mask logic read data latch write drivers column decoder bank0 memory array (8,192 x 2,048 x 4) bank0 row- address latch & decoder 8,192 sense amplifiers bank control logic dq0- dq3 4 4 data input register data output register 4 12 bank1 bank2 bank3 13 11 2 1 1 2 refresh counter
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 8 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram general description figure 2: 32 meg x 8 sdram functional block diagram 13 ras# cas# row- address mux clk cs# we# cke control logic column- address counter/ latch mode register 10 command decode a0?a12, ba0, ba1 dqm 13 address register 15 1,024 (x8) 8,192 i/o gating dqm mask logic read data latch write drivers column decoder bank0 memory array (8,192 x 1,024 x 8) bank0 row- address latch & decoder 8,192 sense amplifiers bank control logic dq0? dq7 8 8 data input register data output register 8 12 bank1 bank2 bank3 13 10 2 1 1 2 refresh counter
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 9 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram general description figure 3: 16 meg x 16 sdram functional block diagram 13 ras# cas# row- address mux clk cs# we# cke control logic column- address counter/ latch mode register 9 command decode a0?a12, ba0, ba1 dqml, dqmh 13 address register 15 512 (x16) 8,192 i/o gating dqm mask logic read data latch write drivers column decoder bank0 memory array (8,192 x 512 x 16) bank0 row- address latch & decoder 8,192 sense amplifiers bank control logic dq0? dq15 16 16 data input register data output register 16 12 bank1 bank2 bank3 13 9 2 2 2 2 refresh counter
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 10 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram pin/ball assignments and descriptions pin/ball assignments and descriptions figure 4: 54-pin tsop assignment (top view) notes: 1. the # symbol indica tes signal is active low. a dash (-) indicates x8 and x4 pin function is same as x16 pin function. v dd dq0 v dd q dq1 dq2 vssq dq3 dq4 v dd q dq5 dq6 vssq dq7 v dd dqml we# cas# ras# cs# ba0 ba1 a10 a0 a1 a2 a3 v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 vss dq15 vssq dq14 dq13 v dd q dq12 dq11 vssq dq10 dq9 v dd q dq8 vss nc dqmh clk cke a12 a11 a9 a8 a7 a6 a5 a4 vss x8 x16 x16 x8 x4 x4 - dq0 - nc dq1 - nc dq2 - nc dq3 - nc - nc - - - - - - - - - - - - - nc - nc dq0 - nc nc - nc dq1 - nc - nc - - - - - - - - - - - - - dq7 - nc dq6 - nc dq5 - nc dq4 - nc - - dqm - - - - - - - - - - - - nc - nc dq3 - nc nc - nc dq2 - nc - - dqm - - - - - - - - - - -
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 11 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram pin/ball assignments and descriptions figure 5: 60-ball fbga assignment (top view) note: fbga pin symbol, type, and descriptions are identical to the listing in table 4 on page 13. a b c d e f g h j k l m n p r 1 2 3 4 5 6 7 8 depopulated balls nc vss nc vssq v dd q dq3 nc nc nc vssq v dd q dq2 nc nc nc vss nc dqm nc ck a12 cke a11 a9 a8 a7 a6 a5 a4 vss v dd nc v dd q nc dq0 vssq nc nc v dd q nc dq1 vssq nc nc v dd nc we# cas# ras# nc nc cs# ba1 ba0 a0 a10 a2 a1 v dd a3 a b c d e f g h j k l m n p r 1 2 3 4 5 6 7 8 depopulated balls dq7 vss nc vssq v dd q dq6 dq5 nc nc vssq v dd q dq4 nc nc nc vss nc dqm nc ck a12 cke a11 a9 a8 a7 a6 a5 a4 vss v dd dq0 v dd q nc dq1 vssq nc dq2 v dd q nc dq3 vssq nc nc v dd nc we# cas# ras# nc nc cs# ba1 ba0 a0 a10 a2 a1 v dd a3 64 meg x 4 sdram 8mm x 16mm ?fb? 32 meg x 8 sdram 8mm x 16mm ?fb?
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 12 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram pin/ball assignments and descriptions figure 6: 54-ball fbga assignment (top view) notes: 1. the balls at a4, a5, and a6 are absent from the physical pac kage. they are in cluded to illus- trate that rows 4, 5, and 6 exis t, but contain no solder balls. a b c d e f g h j 1 2 3 4 5 6 7 89 depopulated balls vss dq15 dq14 dq13 dq12 dq11 dq10 dq9 dq8 nc udqm clk a12 a11 a8 a7 vss a5 v ss q v dd q v ss q v dd q vss cke a9 a6 a4 v dd q vssq v dd q v ss q v dd cas# ba0 a0 a3 dq0 v dd dq2 dq1 dq4 dq3 dq6 dq5 ldqm dq7 ras# we# ba1 cs# a1 a10 a2 v dd
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 13 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram pin/ball assignments and descriptions table 4: 54-pin tsop descriptions pin numbers symbol type description 38 clk input clock: clk is driven by the system clock. all sdram input signals are sampled on the positive edge of cl k. clk also increm ents the internal burst counter and controls the output registers. 37 cke input clock enable: cke activates (high) an d deactivates (low) the clk signal. deactivating the clock provides precharge power-down and self refresh operation (all banks idle), active power-down (row active in any bank), or clock suspend operatio n (burst/access in progress). cke is synchronous except after the device enters power-down and self refresh modes, where cke become s asynchronous until after exiting the same mode. the input buffers, including clk, are disabled during power-down and self refresh modes, providing lo w standby power. cke may be tied high. 19 cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands ar e masked when cs# is registered high, but read/write burst s already in progress w ill continue and dqm operation will retain its dq mask capability while cs# is high. cs# provides for external bank selection on systems with mu ltiple banks. cs# is considered part of the command code. 16, 17, 18 we#, cas#, ras# input command inputs: we#, cas#, and ras# (along with cs#) define the command being entered. 39 x4, x8: dqm input input/output mask: dqm is an input mask signal for write accesses and an output enable signal for read accesses. inpu t data is masked when dqm is sampled high duri ng a write cycle. the output buffers are placed in a high-z state (two-clock latency) when dq m is sampled high during a read cycle. on the x4 and x8 , dqml (pin 15) is a nc and dqmh is dqm. on the x16, dqml co rresponds to dq0?dq7 and dqmh corresponds to dq8?dq15. dqml and dqmh are considered same state when referenced as dqm. 15, 39 x16: dqml, dqmh 20, 21 ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank the active, read, write, or precharge command is being applied. 23?26, 29?34, 22, 35, 36 a0?a12 input address inputs: a0?a12 are sampled during the active command (row- address a0?a12) and read or write command (column-address a0?a9, a11 [x4]; a0?a9 [x8]; a0?a8 [x16]; with a10 defining auto precharge) to select one location out of the memory array in the respective bank. a10 is sampled during a precharge co mmand to determine whether all banks are to be precharged (a10 [high]) or bank selected by (a10 [low]). the address inputs also provide the op-code during a load mode register command. 2, 4, 5, 7, 8, 10, 11, 13, 42, 44, 45, 47, 48, 50, 51, 53 dq0?dq15 x16: i/o data input/output: data bus for x16 (p ins 4, 7, 10, 13, 42, 45, 48, and 51 are ncs for x8; and pins 2, 4, 7, 8, 10, 13, 42, 45, 47, 48, 51, and 53 are ncs for x4). 2, 5, 8, 11, 44, 47, 50, 53 dq0?dq7 x8: i/o data input/output: data bus for x8 (pins 2, 8, 47, 53 are ncs for x4). 5, 11, 44, 50 dq0?dq3 x4: i/o data input/output: data bus for x4. 40 nc ? no connect: this pin should be left unconnected. 3, 9, 43, 49 v dd q supply dq power: dq power to the die for improv ed noise immunity. 6, 12, 46, 52 v ss q supply dq ground: dq ground to the di e for improved noise immunity. 1, 14, 27 v dd supply power supply: +3.3v 0.3v. 28, 41, 54 v ss supply ground.
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 14 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram pin/ball assignments and descriptions table 5: 54-ball and 60-ball fbga descriptions 54-ball fbga 60-ball fbga symbol type description f2 k2 clk input clock: clk is driven by the system clock. all sdram input signals are sampled on the positive edge of clk. clk also incremen ts the internal burst counter and controls the output registers. f3 l2 cke input clock enable: cke activates (high) and deactivates (low) the clk signal. deactivating the clock pr ovides precharge power-down and self refresh operation (all banks idle), active power-down (row active in any bank), or clock suspend operation (burst/access in progress). cke is synchronous except after the device enters power- down and self refresh modes, wher e cke becomes asynchronous until after exiting the same mode. the in put buffers, including clk, are disabled during power-down and self refresh modes, providing low standby power. cke may be tied high. g9 l8 cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all co mmands are masked when cs# is registered high, but read/write bursts alr eady in progress will continue and dqm operation will reta in its dq mask capability while cs# is high. cs# provides for extern al bank selection on systems with multiple banks. cs# is considered part of the command code. f7, f8, f9 j8, k7, j7 cas#, ras#, we# input command inputs: cas#, ras#, and we# (along with cs#) define the command being entered. e8, f1 j2 dqm, ldqm, udqm input input/output mask: dqm is sampled hi gh and is an input mask signal for write accesses and an output enab le signal for read accesses. input data is masked during a write cycle. the output buffers are placed in a high-z state (two-clock latency) when during a read cycle. ldqm corresponds to dq0?dq7; udqm co rresponds to dq8?dq15. ldqm and udqm are considered same state when referenced as dqm. g7, g8 m8, m7 ba0, ba1 input bank address input(s): ba0 and ba1 define to which bank the active, read, write, or precharge command is being applied. these balls also provide the op-code during a load mode register command. h7, h8, j8, j7, j3, j2, h3, h2, h1, g3, h9, g2, g1 n7, p8, p7, r8, r1, p2, p1, n2, n1, m2, n8, m1, l1 a0?a12 input address inputs: a0?a12 are sample d during the active command (row-address a0?a12) and read or write command (column-address a0?a9, a11 [x4]; a0?a9 [x8]; a0?a 8 [x16]; with a10 defining auto precharge) to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether all banks are to be precharged (a10 high) or bank selected by ba0, ba1 (low). the ad dress inputs also provide the op- code during a load mode register command. a8, b9, b8, c9, c8, d9, d8, e9, e1, d2, d1, c2, c1, b2, b1, a2 dq0?dq15 i/o data input/output: data bus. c7, f7, f2, c2 dq0?dq3 (x4) i/o data input/output: data bus. a8, c7, d8, f7, f2, d1, c2, a1 dq0?dq7 (x8) i/o data input/output: data bus. e2 nc ? no connect: these balls sh ould be left unconnected.
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 15 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram functional description functional description in general, the 256mb sdrams (16 meg x 4 x 4 banks, 8 meg x 8 x 4 banks, and 4 meg x 16 x 4 banks) are quad-bank drams that operat e at 3.3v and include a synchronous inter- face (all signals are registered on the positive edge of the clock signal, clk). each of the x4?s 67,108,864-bit banks is organized as 8,192 rows by 2,048 columns by 4 bits. each of the x8?s 67,108,864-bit banks is organized as 8,192 rows by 1,024 columns by 8 bits. each of the x16?s 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits. read and write accesses to the sdram are bu rst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the ba nk and row to be accessed (ba0 and ba1 select the bank, a0?a12 select the row). th e address bits (x4: a0?a9, a11; x8: a0?a9; x16: a0?a8) registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the sdram must be initialized. the following sections provide detailed information covering device initialization, register definition, command descriptions, and device operation. initialization sdrams must be powered up and initiali zed in a predefined manner. operational procedures other than those specified may resu lt in undefined operation. after power is applied to v dd and v dd q (simultaneously) and the cloc k is stable (stable clock is defined as a signal cycling wi thin timing constraints specified for the clock pin), the sdram requires a 100s delay prior to is suing any command other than a command a1, a8, b1, b8, d1, d2, d7, d8, e1, e8, g1, g2, g7, g8, h1, h8, j1, k1, k8, l7 nc x4 no connect: these balls sh ould be left unconnected. g1 is a no connect for this part, but may be used as a12 in future designs. b1, b8, d2, d7, e1, e8, g1, g2, g7, g8, h1, h8, j1, k1, k8, l7 nc x8 no connect: these balls sh ould be left unconnected. g1 is a no connect for this part, but may be used as a12 in future designs. a7, b3, c7, d3 b7, c1, e7, f1 v dd q supply dq power: dq power to the die for improv ed noise immunity. a3, b7, c3, d7 b2, c8, e2, f8 v ss q supply dq ground: dq ground to the die for improved noise immunity. a9, e7, j9 a7, r7 v dd supply power supply: voltage dependent on option. a1, e3, j1 a2, h2, r2 v ss supply ground. table 5: 54-ball and 60-ball fbga descriptions (continued) 54-ball fbga 60-ball fbga symbol type description
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 16 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram functional description inhibit or nop. starting at some point during this 100s period and continuing at least through the end of this period, comman d inhibit or nop commands must be applied. after the 100s delay has been satisfied wi th at least one command inhibit or nop command having been applied, a precharge command should be applied. all banks must then be precharged, thereby placing the device in the all banks idle state. once in the idle state, at least two auto re fresh cycles must be performed. after the auto refresh cycles are complete, the sdram is ready for mode register program- ming. because the mode register will power up in an unknown state, it must be loaded prior to applying any operational command. if desired, the two auto refresh commands can be issued after the lmr command. the recommended power-up sequence for sdrams: 1. simultaneously apply power to v dd and v dd q. 2. assert and hold cke at a lvttl logic low since all inputs and outputs are lvttl- compatible. 3. provide stable clock signal. stable clock is defined as a signal cycling within timing constraints specified for the clock pin. 4. wait at least 100s prior to issuing any command other than a command inhibit or nop. 5. starting at some point during this 100s period, bring cke high. continuing at least through the end of this period, 1 or more command inhibit or nop commands must be applied. 6. perform a precharge all command. 7. wait at least t rp time; during this time nops or deselect commands must be given. all banks will complete their precharge, th ereby placing the device in the all banks idle state. 8. issue an auto refresh command. 9. wait at least t rfc time, during which only nops or command inhibit commands are allowed. 10. issue an auto refresh command. 11. wait at least t rfc time, during which only nops or command inhibit commands are allowed. 12. the sdram is now ready for mode register programming. because the mode register will power up in an unknown state, it should be loaded with desired bit values prior to applying any operational command. using the lmr command, program the mode register. the mode register is progra mmed via the mode register set command with ba1 = 0, ba0 = 0 and retains the stored information until it is programmed again or the device loses power. not programming the mode register upon initialization will result in default settings which may not be desired. outputs are guaranteed high-z after the lmr command is issued. outputs sh ould be high-z already before the lmr command is issued. 13. wait at least t mrd time, during which only nop or deselect commands are allowed. at this point the dram is ready for any valid command. note: if desired, more than two auto refresh commands can be issued in the sequence. after steps 9 and 10 are complete, repeat them until the desired number of auto refresh + t rfc loops is achieved.
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 17 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram functional description register definition mode register the mode register is used to define the spec ific mode of operation of the sdram. this definition includes the selection of bl, a bu rst type, cl, an operating mode, and a write burst mode, as shown in figure 7 on page 18. the mode register is programmed via the load mode register command and will reta in the stored information until it is programmed again or the device loses power. mode register bits m0?m2 specify bl, m3 specifies the type of burst (sequential or inter- leaved), m4?m6 specify cl, m7, and m8 spec ify the operating mode, m9 specifies the write burst mode, and m10 and m11 are reserved for future use. address a12 (m12) is undefined but should be driven low during loading of the mode register. the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subs equent operation. violating either of these requirements will result in unspecified operation. burst length (bl) read and write accesses to the sdram are burst oriented, with bl being programmable, as shown in figure 7 on page 18. bl determines the maximum number of column loca- tions that can be accessed for a given read or write command. burst lengths of 1, 2, 4, or 8 locations are available for both the sequ ential and the interleaved burst types, and a full-page burst is available for the sequential mode. the full-page burst is used in conjunction with the burst terminate command to generate arbitrary bls. reserved states cannot be used, because unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to bl is effectively selected. all accesses for that burst take pl ace within this block, meaning that the burst will wrap within the block if a boundary is re ached. the block is uniquely selected by a1? a9, a11 (x4), a1?a9 (x8) or a1?a8 (x16) when bl = 2; by a2?a9, a11 (x4), a2?a9 (x8) or a2?a8 (x16) when bl = 4; and by a3?a9, a11 (x 4), a3?a9 (x8) or a3?a8 (x16) when bl = 8. the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. full-page bursts wrap within the page if the boundary is reached.
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 18 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram functional description figure 7: mode register definition operating mode the normal operating mode is selected by se tting m7 and m8 to zero; the other combi- nations of values for m7 and m8 are reserved for future use and/or test modes. the programmed bl applies to both read and write bursts. test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. write burst mode when m9 = 0, bl programmed via m0?m2 applies to both read and write bursts; when m9 = 1, the programmed bl applies to read bursts, but write accesses are single- location (nonburst) accesses. m3 = 0 1 2 4 8 reserved reserved reserved full page m3 = 1 1 2 4 8 reserved reserved reserved reserved operating mode standard operation all other states reserved 0 ? 0 ? defined ? 0 1 burst type sequential interleaved cas latency reserved reserved 2 3 reserved reserved reserved reserved burst length m0 0 1 0 1 0 1 0 1 burst length cas latency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m6-m0 m8 m7 op mode a10 a11 10 11 reserved wb 0 1 write burst mode programmed burst length single location access m9 program ba1, ba0 = ?0, 0? to ensure compatibility with future devices. a12 12
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 19 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram functional description burst type accesses within a given burst may be programme d either to be sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses with in a burst is determined by bl, the burst type, and the starting column address, as shown in table 6. notes: 1. for full-page accesses: y = 2,048 (x4); y = 1,024 (x8); y = 512 (x16). 2. for bl = 2, a1?a9, a11 (x4); a1?a9 (x8); or a1?a8 (x16) select the block-of-two burst; a0 selects the starting colu mn within the block. 3. for bl = 4, a2?a9, a11 (x4); a2?a9 (x8); or a2?a8 (x16) select the block-of-four burst; a0? a1 select the starting co lumn within the block. 4. for bl = 8, a3?a9, a11 (x4); a3?a9 (x8); or a3 ?a8 (x16) select the block-of-eight burst; a0? a2 select the starting co lumn within the block. 5. for a full-page burst, the full row is selected and a0?a9, a11 (x4); a0?a9 (x8); or a0?a8 (x16) select the starting column. 6. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. for bl = 1, a0?a9, a11 (x4); a0?a9 (x8); or a0?a8 (x16) select the unique column to be accessed, and mode register bit m3 is ignored. cas latency (cl) cl is the delay, in clock cycles, between the registration of a read command and the availability of the first piece of output data. the latency can be set to two or three clocks. table 6: burst definition burst length starting column address order of accesses within a burst type = sequential type = interleaved 2 a0 0 0-1 0-1 1 1-0 1-0 4a1 a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8a2a1 a0 00 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 00 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 01 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 01 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 10 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 10 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 11 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 11 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full page (y) n = a0?a11/9/8 (location 0?y) cn, cn + 1, cn + 2 cn + 3, cn + 4... ?cn - 1, cn? not supported
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 20 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram functional description if a read command is registered at clock edge n and the latency is m clocks, the data will be available by clock edge n + m . the dqs will start driving as a result of the clock edge one cycle earlier ( n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m . for example, assuming that the clock cycle time is such that all relevant access time s are met, if a read command is registered at t0 and the latency is programmed to two clocks, the dqs wi ll start driving after t1 and the data will be valid by t2, as shown in figure 8. table 7 on page 21 indicates the operating frequen- cies at which each cl setting can be used. reserved states cannot be used as unknown operation or incompatibility with future versions may result. figure 8: cas latency clk dq t2 t1 t3 t0 cl = 3 t lz d out t oh command nop read t ac nop t4 nop don?t care undefined clk dq t2 t1 t3 t0 cl = 2 t lz d out t oh command nop read t ac nop
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 21 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram functional description notes: 1. -6a speed grade supports latency of 3-3-3 cycles (cas latency- t rcd- t rp) at 167 mhz (max). 2. -7e speed grade supports latency of 2-2-2 cycles at 133 mhz (max). table 7: cas latency speed allowable operating frequency (mhz) cl = 2 cl = 3 -6a 1 133 167 -7e 2 133 143 -75 100 133
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 22 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram commands commands truth table 1 provides a quick reference of available commands. this is followed by a written description of each command. three additional truth tables appear following ?operations? on page 25; these tables prov ide current state/next state information. notes: 1. cke is high for all comma nds shown except self refresh. 2. a0?a11 define the op-code wr itten to the mode register, an d a12 should be driven low. 3. a0?a12 provide row address, and ba0, ba 1 determine which bank is made active. 4. a0?a9, a11 (x4); a0?a9 (x8); or a0?a8 (x16) provide column address; a10 high enables the auto precharge feature (nonpe rsistent), while a10 low disa bles the auto precharge fea- ture; ba0, ba1 determine which bank is being read from or written to. 5. a10 low: ba0, ba1 determine the bank being precharged. a10 high: all banks precharged and ba0, ba1 are ?don?t care.? 6. this command is auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are ?don?t care? except for cke. 8. activates or deactivates the dqs during wri tes (zero-clock delay) and reads (two-clock delay). the command inhibit the command inhibit function prevents new commands from being executed by the sdram, regardless of whether the clk signal is enabled. the sdram is effectively dese- lected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to perform a nop to an sdram that is selected (cs# is low). this prevents unwant ed commands from being registered during idle or wait states. operations al ready in progress are not affected. table 8: truth table 1 ? commands and dqm operation note: 1 applies to the entire table name (function) cs# ras# cas# we# dqm addr dqs notes command inhibit (nop) hxxxx x x no operation (nop) l hhhx x x active (select bank and activate row) llhhxbank/rowx 3 read (select bank and column, and start read burst) lhlhl/h8bank/colx 4 write (select bank and column, and start write burst) l h l l l/h8 bank/col valid 4 burst terminate lhhlx x active precharge (deactivate row in bank or banks) llhlxcode x 5 auto refresh or self refresh (enter self refresh mode) lllhx x x6, 7 load mode register llllxop-codex 2 write enable/output enable ????l ? active8 write inhibit/output high-z ????h ?high-z8
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 23 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram commands load mode register the mode register is loaded via inputs a0?a11 (a12 should be driven low.) see ?register definition? on page 17. the load mode register command can only be issued when all banks are idle, and a subsequent exec utable command cannot be issued until t mrd is met. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a12 selects the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the ba0, ba1 inputs selects the bank, and th e address provided on inputs a0?a9, a11 (x4), a0?a9 (x8), or a0?a8 (x16) selects the st arting column location. the value on input a10 determines whether auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subs equent accesses. read data appears on the dqs subject to the logic level on the dqm inputs two clocks earlier. if a given dqm signal was registered high, the corresponding dq s will be high-z two clocks later; if the dqm signal was registered low, the dqs will provide valid data. write the write command is used to initiate a burst write access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a9; a11 (x4); a0?a9 (x8); or a0?a8 (x16) selects the st arting column location. the value on input a10 determines whether auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subseq uent accesses. input data appearing on the dqs is written to the memory array subject to the dqm input logic level appearing coin- cident with the data. if a given dqm signal is registered low, the corresponding data will be written to memory; if the dqm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time ( t rp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as ?don?t care.? after a bank has been precharged, it is in the idle state and must be acti- vated prior to any read or write commands being issued to that bank.
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 24 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram commands auto precharge auto precharge is a feature that performs the same individual-bank precharge function described above, without requiring an explic it command. this is accomplished by using a10 to enable auto precharge in conjunctio n with a specific read or write command. a precharge of the bank/row that is addr essed with the read or write command is automatically performed upon completion of the read or write burst, except in the full-page burst mode, where auto precharge does not apply. auto precharge is nonper- sistent in that it is either enabled or di sabled for each individual read or write command. auto precharge ensures that the precharge is in itiated at the earliest valid stage within a burst. the user must not issue another comma nd to the same bank until the precharge time ( t rp) is completed. this is determined as if an explicit precharge command was issued at the earliest possible time, as desc ribed for each burst type in ?operations? on page 25. burst terminate the burst terminate command is used to truncate either fixed-length or full-page bursts. the most recently registered read or write command prior to the burst terminate command will be truncated, as shown in ?operations? on page 25. the burst terminate command does not prechar ge the row; the row will remain open until a precharge command is issued. figure 9: terminating a write burst note: dqm is low. auto refresh auto refresh is used during normal operation of the sdram and is analogous to cas#-before-ras# (cbr) refresh in conventional drams. this command is nonper- sistent, so it must be issued each time a refresh is required. all active banks must be precharged prior to issuing an auto refresh command. the auto refresh command should not be issued until the minimum t rp has been met after the precharge command, as shown in ?operations? on page 25. the addressing is generated by the internal refresh controller. this makes the address bits a ?don?t care? during an auto refresh command. the 256mb sdram requires 8,192 auto refresh cycles every 64ms ( t ref), regardless of width option. providing a don?t care clk dq t2 t1 t0 command address bank, col n write burst terminate next command d in n (address) (data) transitioning data
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 25 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram operations distributed auto refresh command every 7 .81s will meet the refresh requirement and ensure that each row is refreshed. alternatively, 8,192 auto refresh commands can be issued in a burst at the minimum cycle rate ( t rfc), once every 64ms. self refresh the self refresh command can be used to reta in data in the sdram, even if the rest of the system is powered down. when in the self refresh mode, the sdram retains data without external clocking. the self refresh command is initiated like an auto refresh command except cke is disabled (low). after the self refresh co mmand is registered, all the inputs to the sdram become a ?don?t care? with the exception of cke, which must remain low. after self refresh mode is engaged, the sdram provides its own internal clocking, causing it to perform its own auto refresh cycles. the sdram must remain in self refresh mode for a minimum period equal to t ras and may remain in self refresh mode for an indefinite period beyond that. the procedure for exiting self refresh requires a sequence of commands. first, clk must be stable (stable clock is defi ned as a signal cycling within timing constraints specified for the clock pin) prior to cke going back high. after cke is high, the sdram must have nop commands issued (a minimum of two clocks) for t xsr because time is required for the completion of an y internal refresh in progress. upon exiting the self refresh mode, auto refresh commands must be issued every 7.81s or less as both self refresh and auto refresh utilize the row refresh counter. operations bank/row activation before any read or write commands can be issued to a bank within the sdram, a row in that bank must be ?opened.? this is accomplished via the active command, which selects both the bank and the row to be activated (see figure 10 on page 26). after opening a row (issuing an active co mmand), a read or write command may be issued to that row, subject to the t rcd specification. t rcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be entered. for example, a t rcd specification of 20ns with a 125 mhz clock (8ns period) results in 2.5 clocks, rounded to 3. this is reflected in figure 11 on page 26, which covers any case where 2 < t rcd (min)/ t ck 3. (the same procedure is used to convert other specification limits from time units to clock cycles.) a subsequent active command to a different row in the same bank can only be issued after the previous active row has been ?closed? (precharged). the minimum time interval between successive active comma nds to the same bank is defined by t rc. a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the minimum time interval between successive active co mmands to different banks is defined by t rrd.
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 26 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram operations figure 10: activating a specific row in a specific bank figure 11: example: meeting t rcd (min) when 2 < t rcd (min)/ t ck 3 reads read bursts are initiated with a read co mmand, as shown in figure 12 on page 27. the starting column and bank addresses are provided with the read command, and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the generic read commands used in the following illustrations, auto precharge is disabled. during read bursts, the valid data-out elem ent from the starting column address will be available following cl after the read command. each subseque nt data-out element will be valid by the next positive clock edge. figure 13 on page 28 shows general timing for each possible cl setting. upon completion of a burst, assuming no other commands have been initiated, the dqs will go high-z. a full-page burst will continue until terminated. (at the end of the page, it will wrap to the start address and continue.) data from any read burst may be truncate d with a subsequent read command, and data from a fixed-length read burst may be immediately followed by data from a read command. in either case, a continuous flow of data can be maintained. the first data cs# we# cas# ras# cke clk a0?a12 row address don?t care high ba0, ba1 bank address clk t2 t1 t3 t0 t command nop active read or write t4 nop rcd don?t care
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 27 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram operations element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burs t that is being truncated. the new read command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = cl - 1. this is shown in figure 13 on page 28 fo r cl = 2 and cl = 3; data element n + 3 is either the last of a burst of four or the last desi red of a longer burst. the 256mb sdram uses a pipelined architecture and therefore does not require the 2 n rule associated with a prefetch architecture. a read command can be initiated on any clock cycle following a previous read command. full-speed random read accesses can be performed to the same bank, as shown in figure 14 on page 29, or each subsequent read may be performed to a different bank. figure 12: read command cs# we# cas# ras# cke clk column address x4 a0?a9: x8 a0?a8: x16 a0?a9, a11: a10 ba0, ba1 don?t care high enable auto precharge disable auto precharge bank address a12: x4 a11, a12: x8 a9, a11, a12: x16
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 28 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram operations figure 13: consecutive read bursts note: each read command may be to any bank. dqm is low. don?t care clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read x = 1 cycle cl = 2 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read nop t7 x = 2 cycles cl = 3 transitioning data
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 29 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram operations figure 14: random read accesses note: each read command may be to any bank. dqm is low. data from any read burst may be truncate d with a subsequent write command, and data from a fixed-length read burst may be immediately followed by data from a write command (subject to bus turnaround limitations). the write burst may be initiated on the clock edge immediately following the last (or last desired) data element from the read burst, provided that i/o cont ention can be avoided. in a given system design, there may be a possibility that the device driving the input data will go low-z before the sdram dqs go high-z. in this case, at least a single-cycle delay should occur between the last read data and the write command. the dqm input is used to avoid i/o contention, as shown in figure 15 and figure 16 on page 30. the dqm signal must be asserted (hig h) at least two clocks prior to the write command (dqm latency is two clocks for output buffers) to suppress data-out from the read. once the write command is registered, the dqs will go high-z (or remain high-z), regardless of the state of the dqm signal; provided the dqm was active on the clock just prior to the write command that truncated the read command. if not, the second write will be an invalid write. fo r example, if dqm was low during t4 in figure 11 on page 26, then the writes at t5 and t7 would be valid, while the write at t6 would be invalid. clk dq t2 t1 t4 t3 t6 t5 t0 command address read nop nop bank, col n don?t care d out n d out a d out x d out m read read read nop bank, col a bank, col x bank, col m clk dq d out n t2 t1 t4 t3 t5 t0 command address read nop bank, col n d out a d out x d out m read read read nop bank, col a bank, col x bank, col m cl = 2 cl = 3 transitioning data
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 30 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram operations the dqm signal must be de-asserted prior to the write command (dqm latency is zero clocks for input buffers) to ensure that the written data is not masked. figure 10 on page 26 shows the case where the clock frequency allows for bus contention to be avoided without adding a nop cycle, and figure 16 shows the case where the additional nop is needed. figure 15: read-to-write note: cl = 3 is used for illustration. the read command may be to any bank, and the write command may be to any bank. if a burst of one is used, then dqm is not required. figure 16: read-to-write with extra clock cycle note: cl = 3 is used for illustration. the read command may be to any bank, and the write command may be to any bank. a fixed-length read burst may be followed by, or truncated with, a precharge command to the same bank (provided that au to precharge was not activated), and a full- page burst may be truncated with a precharge command to the same bank. the precharge command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = cl - 1. this is shown in figure 17 on page 31 for each possible cl; data element n + 3 is either the last of a burst of four or the last desired read nop nop write nop clk t2 t1 t4 t3 t0 dqm dq d out n command d in b address bank, col n bank, col b ds t hz t t ck don?t care read nop nop nop nop dqm clk dq d out n t2 t1 t4 t3 t0 command address bank, col n write bank, col b t5 ds t hz t transitioning data d in b
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 31 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram operations of a longer burst. following the precharg e command, a subsequent command to the same bank cannot be issued until t rp is met. note that part of the row precharge time is hidden during the access of the last data element(s). in the case of a fixed-length burst being executed to completion, a precharge command issued at the optimum time (as desc ribed above) provides the same operation that would result from the same fixed-length burst with auto precharge. the disadvan- tage of the precharge command is that it requires command and address buses to be available at the appropriate time to issue the command; the advantage of the precharge command is that it can be used to truncate fixed-length or full-page bursts. full-page read bursts can be truncated with the burst terminate command, and fixed-length read bursts may be truncated with a burst terminate command, provided that auto precharge was not activated. the burst terminate command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = cl - 1. this is shown in figure 18 on page 32 for each possible cl; data element n + 3 is the last desired data element of a longer burst. figure 17: read-to-precharge note: dqm is low. don?t care clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop nop d out n + 1 d out n + 2 d out n + 3 precharge active t rp t7 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop nop d out n + 1 d out n + 2 d out n + 3 precharge active t rp t7 x = 1 cycle cl = 2 cl = 3 x = 2 cycles bank a , col n bank a , row bank ( a or all) bank a , col n bank a , row bank ( a or all) transitioning data
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 32 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram operations figure 18: terminating a read burst note: dqm is low. writes write bursts are initiated with a write command, as shown in figure 19 on page 33. the starting column and bank addresses ar e provided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at th e completion of the burst. for the generic write commands used in the following illustrations, auto precharge is disabled. during write bursts, the first valid data-in element will be registered coincident with the write command. subsequent data elements will be registered on each successive positive clock edge. upon completion of a fixed-length burst, assuming no other commands have been initiated, the dqs will remain high-z, and any additional input data will be ignored (see figure 20 on page 33). a full-page burst will continue until terminated. (at the end of the page, it will wrap to the start address and continue.) clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop t7 don?t care clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop x = 1 cycle cl = 2 cl = 3 x = 2 cycles transitioning data
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 33 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram operations figure 19: write command figure 20: write burst note: bl = 2. dqm is low. data for any write burst may be truncate d with a subsequent write command, and data for a fixed-length write burst may be immediately followed by data for a write command. the new write command can be issued on any clock following the previous write command, and the data provided coin cident with the new command applies to the new command. an example is shown in figure 21 on page 34. data n + 1 is either the last of a burst of two or the last desired of a longer burst. the 256mb sdram uses a pipe- lined architecture and therefore does not require the 2 n rule associated with a prefetch architecture. a write command can be initiated on any clock cycle following a previous write command. full-speed random write acce sses within a page can be performed to the same bank, as shown in figure 22 on page 34, or each subsequent write may be performed to a different bank. cs# we# cas# ras# cke clk column address a10 high enable auto precharge disable auto precharge a0?a9, a11: x4 a0?a9: x8 a0?a8: x16 a12: x4 a11, a12: x8 a9, a11, a12: x16 ba0, ba1 bank address clk dq d in n t2 t1 t3 t0 command address nop nop don?t care write d in n + 1 nop bank, col n transitioning data
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 34 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram operations data for any write burst may be truncate d with a subsequent read command, and data for a fixed-length write burst may be immediately followed by a read command. after the read command is registered, the data inputs will be ignored, and writes will not be executed. an example is shown in figure 23. data n + 1 is either the last of a burst of two or the last desired of a longer burst. figure 21: write-to-write note: dqm is low. each write command may be to any bank. figure 22: random write cycles figure 23: write-to-read data for a fixed-length write burst may be followed by, or truncated with, a precharge command to the same bank (provided that auto precharge was not acti- vated), and a full-page write burst may be truncated with a precharge command to the same bank. the precharge command should be issued t wr after the clock edge at clk dq t2 t1 t0 command address nop write write bank, col n bank, col b d in n d in n + 1 d in b clk dq d in n t2 t1 t3 t0 command address write bank, col n d in a d in x d in m write write write bank, col a bank, col x bank, col m don?t care clk dq t2 t1 t3 t0 command address nop write bank, col n d in n d in n + 1 d out b read nop nop bank, col b nop d out b + 1 t4 t5 transitioning data
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 35 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram operations which the last desired input data element is registered. the auto precharge mode requires a t wr of at least one clock plus time, rega rdless of frequency. in addition, when truncating a write burst, the dqm signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the precharge command. an example is shown in figure 24. data n + 1 is either the last of a burst of two or the last desired of a longer burst. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. the precharge is issued coincident with the second clock (see figure 24). in the case of a fixed-length burst being executed to completion, a precharge command issued at the optimum time (as desc ribed above) provides the same operation that would result from the same fixed-length burst with auto precharge. the disadvan- tage of the precharge command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the precharge command is that it can be used to truncate fixed-length or full-page bursts. fixed-length or full-page write bursts can be truncated with the burst terminate command. when truncating a write burst, the input data applied coincident with the burst terminate command will be ignored. the last data written (provided that dqm is low at that time) will be the input data applied one clock previous to the burst terminate command. this is shown in figure 9 on page 24, where data n is the last desired data element of a longer burst. figure 24: write-to-precharge note: dqm could remain low in this example if the write burst is a fixed length of two. don?t care dqm clk dq t2 t1 t4 t3 t0 command address bank a , col n t5 nop write precharge nop nop d in n d in n + 1 active t rp bank ( a or all) t wr bank a , row dqm dq command address bank a , col n nop write precharge nop nop d in n d in n + 1 active t rp bank ( a or all) t wr bank a , row t6 nop nop t wr @ t clk 15ns t wr = t clk < 15ns transitioning data
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 36 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram operations precharge the precharge command (see figure 25 on page 36) is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) wi ll be available for a subsequent row access some specified time ( t rp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged , inputs ba0, ba1 select the bank. when all banks are to be precharged, inputs ba0, ba1 ar e treated as ?don?t care.? after a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. power-down power-down occurs if cke is registered low coincident with a nop or command inhibit when no accesses are in progress. if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and outp ut buffers, excluding cke, for maximum power savings while in standby. the device may not remain in the power-down state longer than the refresh period (64ms) sinc e no refresh operatio ns are performed in this mode. the power-down state is exited by regi stering a nop or command inhibit and cke high at the desired clock edge (meeting t cks). see figure 26 on page 37. figure 25: precharge command don?t care cs# we# cas# ras# cke clk a10 high all banks bank selected a0-a9, a11, a12 ba0, ba1 bank address
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 37 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram operations figure 26: power-down clock suspend the clock suspend mode occurs when a column access/burst is in progress and cke is registered low. in the clock suspend mode, the internal clock is deactivated, ?freezing? the synchronous logic. for each positive clock edge on which cke is sampled low, the next internal positive clock edge is suspended. any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the dq pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (see examples in figure 27 and figure 28 on page 38.) clock suspend mode is exited by registering cke high; the internal clock and related operation will resume on the subsequent positive clock edge. figure 27: clock suspend during write burst don?t care t ras t rcd t rc all banks idle input buffers gated off exit power-down mode. ( ) ( ) ( ) ( ) ( ) ( ) t cks > t cks command nop active enter power-down mode. nop clk cke ( ) ( ) ( ) ( ) don?t care d in command address write bank, col n d in n nop nop clk t2 t1 t4 t3 t5 t0 cke internal clock nop d in n + 1 d in n + 2 transitioning data
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 38 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram operations figure 28: clock suspend during read burst note: for this example, cl = 2, bl = 4 or greater, and dqm is low. burst read/single write mode the burst read/single write mode is entered by programming the write burst mode bit (m9) in the mode register to a logic 1. in this mode, all write commands result in the access of a single column location (burst of one), regardless of the programmed bl. read commands access columns according to the programmed bl and sequence, just as in the normal mode of operation (m9 = 0). concurrent auto precharge an access command (read or write) to an other bank while an access command with auto precharge enabled is executing is not allowed by sdrams, unless the sdram supports concurrent auto precharge. mi cron sdrams support concurrent auto precharge. four cases where concurrent auto precharge occurs are defined below. read with auto precharge ? interrupted by a read (with or with out auto precharge): a read to bank m will inter- rupt a read on bank n , cl later. the precharge to bank n will begin when the read to bank m is registered (figure 29 on page 39). ? interrupted by a write (with or with out auto precharge): a write to bank m will interrupt a read on bank n when registered. dqm should be used two clocks prior to the write command to prevent bus contention. the precharge to bank n will begin when the write to bank m is registered (figure 30 on page 39). write with auto precharge ? interrupted by a read (with or with out auto precharge): a read to bank m will inter- rupt a write on bank n when registered, with the data -out appearing cl later. the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write to bank n will be data-in registered one clock prior to the read to bank m (figure 31 on page 40). don?t care clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 cke internal clock nop transitioning data
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 39 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram operations ? interrupted by a write (with or with out auto precharge): a write to bank m will interrupt a write on bank n when registered. the precharge to bank n will begin after t wr is met, where t wr begins when the write to bank m is registered. the last valid data write to bank n will be data registered one clock prior to a write to bank m (figure 32 on page 40). figure 29: read with auto precharge interrupted by a read notes: 1. dqm is low. figure 30: read with auto precharge interrupted by a write notes: 1. dqm is high at t2 to prevent d out - a + 1 from contending with d in - d at t4. don?t care clk dq d out a t2 t1 t4 t3 t6 t5 t0 command read - ap bank n nop nop nop nop d out a + 1 d out d d out d + 1 nop t7 bank n cl = 3 (bank m ) bank m address idle nop bank n , col a bank m , col d read - ap bank m internal states t page active read with burst of 4 interrupt burst, precharge page active read with burst of 4 precharge rp - bank n t rp - bank m cl = 3 (bank n ) transitioning data clk dq d out a t2 t1 t4 t3 t6 t5 t0 command nop nop nop nop d in d + 1 d in d d in d + 2 d in d + 3 nop t7 bank n bank m address idle nop dqm bank n , col a bank m , col d write - ap bank m internal states t page active read with burst of 4 interrupt burst, precharge page active write with burst of 4 write-back rp - bank n t wr - bank m cl = 3 (bank n ) read - ap bank n 1 don?t care transitioning data
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 40 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram operations figure 31: write with auto precharge interrupted by a read notes: 1. dqm is low. figure 32: write with auto pr echarge interrupted by a write notes: 1. dqm is low. don?t care clk dq t2 t1 t4 t3 t6 t5 t0 command write - ap bank n nop nop nop nop d in a + 1 d in a nop nop t7 bank n bank m address bank n , col a bank m , col d read - ap bank m internal states t page active write with burst of 4 interrupt burst, write-back precharge page active read with burst of 4 t t rp - bank m d out d d out d + 1 cl = 3 (bank m ) rp - bank n wr - bank n transitioning data don?t care clk dq t2 t1 t4 t3 t6 t5 t0 command write - ap bank n nop nop nop nop d in d + 1 d in d d in a + 1 d in a + 2 d in a d in d + 2 d in d + 3 nop t7 bank n bank m address nop bank n , col a bank m , col d write - ap bank m internal states t page active write with burst of 4 interrupt burst, write-back precharge page active write with burst of 4 write-back wr - bank n t rp - bank n t wr - bank m transitioning data
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 41 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram operations notes: 1. cke n is the logic state of cke at clock edge n ; cke n - 1 was the state of cke at the previous clock edge. 2. current state is the state of the sd ram immediately prior to clock edge n . 3. command n is the command registered at clock edge n , and action n is a result of command n . 4. all states and sequences not sh own are illegal or reserved. 5. exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that t cks is met). 6. exiting self refresh at clock edge n will put the device in the all banks idle state after t xsr is met. command inhibit or nop co mmands should be issued on any clock edges occurring during the t xsr period. a minimum of two nop commands must be provided during t xsr period. 7. after exiting clock suspend at clock edge n , the device will resume operation and recognize the next command at clock edge n + 1. table 9: truth table 2 ? cke notes 1?4 apply to the entire table cke n - 1 cke n current state command n action n notes l l power-down x maintain power-down self refresh x maintain self refresh clock suspend x mainta in clock suspend l h power-down command inhibit or nop exit power-down 5 self refresh command inhibit or nop exit self refresh 6 clock suspend x exit clock suspend 7 h l all banks idle command inhibi t or nop power-down entry all banks idle auto refresh self refresh entry reading or writing write or nop clock suspend entry h h see table 10 on page 42
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 42 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram operations notes: 1. this table applies when cke n-1 was high and cke n is high (see table 9 on page 41) and after t xsr has been met (if the previous state was self refresh). 2. this table is bank-specific, except where note d, that is, the current state is for a specific bank, and the commands shown are those allowed to be issued to that bank when in that state. exceptions are covered in the notes below. 3. current state definitions: 4. the following states must not be interrupted by a command issued to the same bank. com- mand inhibit or nop commands or allowabl e commands to the other bank should be issued on any clock edge occurring during th ese states. allowable commands to the other bank are determined by its current state and table 10 and according to table 11 on page 44. table 10: truth table 3 ? current state bank n , command to bank n notes 1?6 apply to the en tire table; notes appear below and on page 43 current state cs# ras# cas# we# command (action) notes any hxxx command inhibit (nop/continue previous operation) l hhh no operation (nop/continue previous operation) idle l l h h active (select and activate row) lllh auto refresh 7 llll load mode register 7 llhl precharge 11 row activelhlh read (select column and start read burst) 10 lhl l write (select column and start write burst) 10 llhl precharge (deactivate row in bank or banks) 8 read (auto precharge disabled) lhlh read (select column and start new read burst) 10 lhl l write (select column and start write burst) 10 llhl precharge (truncate read burst, start precharge) 8 lhhl burst terminate 9 write (auto precharge disabled) lhlh read (select column and start read burst) 10 lhl l write (select column an d start new write burst) 10 llhl precharge (truncate write burst, start precharge) 8 lhhl burst terminate 9 idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no regist er accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, wi th auto precharge disabled, and has not yet terminated or been terminated. precharging: starts with registration of a pr echarge command and ends when t rp is met. after t rp is met, the bank will be in the idle state. row activating: starts with registration of an active command and ends when t rcd is met. after t rcd is met, the bank will be in the row active state. read w/auto precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. after t rp is met, the bank will be in the idle state. write w/auto precharge enabled: starts with registration of a writ e command with auto precharge enabled and ends when t rp has been met. after t rp is met, the bank will be in the idle state.
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 43 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram operations 5. the following states must not be inte rrupted by any executable command; command inhibit or nop commands must be applied on each positive cl ock edge during these states. 6. all states and sequences not sh own are illegal or reserved. 7. not bank-specific; require s that all banks are idle. 8. may or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 9. not bank-specific; burst terminate affects th e most recent read or write burst, regard- less of bank. 10. reads or writes listed in the command (act ion) column include reads or writes with auto precharge enabled and reads or wr ites with auto precharge disabled. 11. does not affect the state of the ba nk and acts as a nop to that bank. refreshing: starts with registration of an aut o refresh command and ends when t rc is met. after t rc is met, the sdram will be in the all banks idle state. accessing mode register: starts with registration of a load mode register command and ends when t mrd has been met. after t mrd is met, the sdram will be in the all banks idle state. precharging all: starts with registration of a prec harge all command and ends when t rp is met. after t rp is met, all banks wi ll be in the idle state.
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 44 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram operations notes: 1. this table applies when cke n - 1 was high and cken is high (see table 9 on page 41) and after t xsr has been met (if the previous state was self refresh). 2. this table describes alternate bank operation, except where noted; that is, the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given comma nd is allowable). exceptions are covered in the notes below. 3. current state definitions: 4. auto refresh, self refresh, and load mo de register commands may only be issued when all banks are idle. table 11: truth table 4 ? current state bank n , command to bank m notes 1?6 apply to the en tire table; notes appear below and on page 45 current state cs# ras# cas# we# command (action) notes any hxxx command inhibit (nop/continue previous operation) l hhh no operation (nop/continue previous operation) idle xxxx any command otherwise allowed to bank m row activating, active, or precharging llhh active (select and activate row) lhlh read (select column and start read burst) 7 lhl l write (select column and start write burst) 7 llhl precharge read (auto precharge disabled) llhh active (select and activate row) lhlh read (select column and start new read burst) 7, 10 lhl l write (select column and start write burst) 7, 11 llhl precharge 9 write (auto precharge disabled) llhh active (select and activate row) lhlh read (select column and start read burst) 7, 12 lhl l write (select column an d start new write burst) 7, 13 llhl precharge 9 read (with auto precharge) llhh active (select and activate row) lhlh read (select column and start new read burst) 7, 8, 14 lhl l write (select column and start write burst) 7, 8, 15 llhl precharge 9 write (with auto precharge) llhh active (select and activate row) lhlh read (select column and start read burst) 7, 8, 16 lhl l write (select column an d start new write burst) 7, 8, 17 llhl precharge 9 idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no regi ster accesses are in progress. read: a read burst has been initiated, wi th auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. read w/auto precharge enabled: starts with registration of a read command with auto precharge enabled, and ends when t rp has been met. after t rp is met, the bank will be in the idle state. write w/auto precharge enabled: starts with registration of a writ e command with auto precharge enabled, and ends when t rp has been met. after t rp is met, the bank will be in the idle state.
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 45 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram operations 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and sequences not sh own are illegal or reserved. 7. reads or writes to bank m listed in the command (actio n) column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8. concurrent auto precharge: bank n will initiate the auto precharge command when its burst has been interrupted by bank m ?s burst. 9. burst in bank n continues as initiated. 10. for a read without auto precharge interrup ted by a read (with or without auto pre- charge), the read to bank m will interrupt the read on bank n , cl later (see figure 13 on page 28). 11. for a read without auto precharge interrup ted by a write (with or without auto pre- charge), the write to bank m will interrupt the read on bank n when registered (see figures 15 and 16 on page 30). dqm should be used one clock prior to the write command to prevent bus contention. 12. for a write without auto precharge interru pted by a read (with or without auto pre- charge), the read to bank m will interrupt the write on bank n when registered (see figure 23 on page 34), with the data-out appearin g cl later. the last valid write to bank n will be data-in registered one cl ock prior to the read to bank m . 13. for a write without auto precharge interrupt ed by a write (with or without auto pre- charge), the write to bank m will interrupt the write on bank n when registered (see figure 21 on page 34). the last valid write to bank n will be data-in registered one clock prior to the read to bank m . 14. for a read with auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the read on bank n , cl later. the precharge to bank n will begin when the read to bank m is registered (see figure 29 on page 39). 15. for a read with auto precharge interrupted by a write (with or without auto precharge), the write to bank m will interrupt the read on bank n when registered . dqm should be used two clocks prior to the write command to prevent bus contention. the precharge to bank n will begin when the write to bank m is registered (see figure 30 on page 39). 16. for a write with auto precha rge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the write on bank n when registered, with the data-out appearing cl later. the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write to bank n will be data-in regis- tered one clock prior to the read to bank m (see figure 31 on page 40). 17. for a write with auto precha rge interrupted by a write (wit h or without auto precharge), the write to bank m will interrupt the write on bank n when registered. the precharge to bank n will begin after t wr is met, where t wr begins when the write to bank m is regis- tered. the last valid write to bank n will be data registered one clock prior to the write to bank m (see figure 32 on page 40).
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 46 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram electrical specifications electrical specifications stresses greater than those listed in table 12 may cause permanent damage to the device. this is a stress rating only, and functi onal operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to abso lute maximum rating conditio ns for extended periods may affect reliability. temperature and thermal impedance it is imperative that the sdram device?s temperature specifications, shown in table 13 on page 47, be maintained to ensure the junction temperature is in the proper operating range to meet data sheet specifications. an important step in maintaining the proper junction temperature is using the device?s thermal impedances correctly. the thermal impedances are listed in table 14 on page 47 for the applicable die revision and pack- ages being made available. these thermal impedance values vary according to the density, package, and particular design used for each device. incorrectly using thermal impedances can produce significant errors. read micron tech- nical note tn-00-08, ?thermal applications ? prior to using the thermal impedances listed in table 14. to ensure the compatibil ity of current and future designs, contact micron applications engineering to confirm thermal impedance values. the sdram device?s safe junction temperature range can be maintained when the t c specification is not exceeded. in applications where the device?s ambient temperature is too high, use of forced air and/or heat sinks may be required to satisfy the case tempera- ture specifications. table 12: absolute maximum ratings parameter min max units voltage on v dd ; v dd q supply relative to v ss ?1 +4.6 v voltage on inputs, nc, or i/o pins relative to v ss ?1 +4.6 v operating temperature t a (commercial) t a (industrial ?it?) 0 ?40 +70 +85 c c storage temperature (plastic) ?55 +150 c power dissipation ?1w
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 47 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram electrical specifications notes: 1. max operating case temperature, t c , is measured in the center of the package on the top side of the device, as shown in figure 33, figure 34, and figure 35 on page 48. 2. device functionality is not guarant eed if the device exceeds maximum t c during operation. 3. both temperature specific ations must be satisfied. 4. the case temperature should be measured by gluing a thermocouple to the top center of the component. this shou ld be done with a 1mm bead of conductive epoxy, as defined by the jedec eia/jesd51 standards. care should be taken to ensure the thermocouple bead is touching the case. 5. operating ambient temperatur e surrounding the package. notes: 1. for designs expected to last beyond the die revision listed, contact micron applications engineering to confirm thermal impedance values. 2. thermal resistance data is sampled from mult iple lots, and the values should be viewed as typical. 3. these are estimates; actual results may vary. ta bl e 1 3 : te mp er a t ure l im it s parameter symbol min max units notes operating case temperature: commercial industrial t c 0 -40 80 90 c 1, 2, 3, 4 junction temperature: commercial industrial t j 0 -40 85 95 c 3 ambient temperature: commercial industrial t a 0 -40 70 85 c 3, 5 peak reflow temperature t peak ?260c table 14: thermal impedance simulated values die revision package substrate ja (c/w) airflow = 0m/s ja (c/w) airflow = 1m/s ja (c/w) airflow = 2m/s jb (c/w) jc (c/w) d 54-pin tsop 2-layer 81 63.8 57.6 45.3 10.3 4-layer 44 47.3 44.5 39.1 54-ball vfbga 2-layer 64.9 50.8 44.8 31.4 3.2 4-layer 51.5 41.6 38.1 31.4 60-ball fbga 2-layer 67 51.2 47.8 19.7 6.7 4-layer 40.9 35.1 32.2 18.6
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 48 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram electrical specifications figure 33: example temperature test point location, 54-pin tsop: top view figure 34: example temperature test point location, 54-ball vfbga: top view figure 35: example temperature test point location, 60-ball fbga: top view 22.22mm 11.11mm test point 10.1 6 mm 5.08mm 8.00mm 4.00mm test point 7.00mm 14.00mm 8.00mm 4.00mm test point 8.00mm 1 6 .00mm
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 49 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram electrical specifications table 15: dc electrical characteristics and operating conditions notes 1, 5, 6 apply to the entire table; notes appear on page 54; v dd , v dd q = +3.3v 0.3v parameter/condition symbol min max units notes supply voltage v dd , v dd q3 3.6 v input high voltage: logic 1; all inputs v ih 2v dd + 0.3 v 22 input low voltage: logic 0; all inputs v il ?0.3 0.8 v 22 input leakage current: any input 0v vin v dd (all other pins not under test = 0v) i i ?5 5 a output leakage current: dqs are disabled; 0v vout v dd q i oz ?5 5 a output levels: output high voltage (i out = ?4ma) output low voltage (i out = 4ma) v oh 2.4 ? v v ol ?0.4v table 16: i dd specifications and conditions (-6a) notes 1, 5, 6, 11, 13 appl y to the entire table; notes appear on page 54; v dd /v dd q = +3.3v 0.3v parameter/condition symbol -6a units notes operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd 1 135 ma 3, 18, 19, 29 standby current: power-down mode; all device banks idle; cke = low i dd 22ma30 standby current: active mode; cke = high; cs# = high; all device banks active after t rcd met; no accesses in progress i dd 3 40 ma 3, 12, 19, 29 operating current: burst mo de; continuous burst; read or write; all device banks active i dd 4 135 ma 3, 18, 19, 29 auto refresh current: cs# = high; cke = high t rfc = t rfc (min) i dd 5 285 ma 3, 12, 18, 19, 29, 30 t rfc = 8.125s i dd 63.5ma self refresh current: cke 0.2v i dd 72.5ma 4 table 17: i dd specifications and conditions (-7e, -75) notes 1, 5, 6, 11, 13 appl y to the entire table; notes appear on page 54; v dd , v dd q = +3.3v 0.3v parameter/condition symbol max units notes -7e -75 operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd 1 135 125 ma 3, 18, 19, 32 standby current: power-down mode; all banks idle; cke = low i dd 222ma32 standby current: active mode; cke = high; cs# = high; all banks active after t rcd met; no accesses in progress i dd 3 40 40 ma 3, 12, 19, 32 operating current: burst mode; page burst; read or write; all banks active i dd 4 135 135 ma 3, 18, 19, 32 auto refresh current: cs# = high; cke = high t rfc = t rfc (min) i dd 5 285 270 ma 3, 12, 18, 19, 32, 33 t rfc = 7.81s i dd 6 3.53.5ma self refresh current: cke 0.2v standard i dd 72.52.5ma4 low power (l) i dd 71.51.5ma
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 50 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram electrical specifications table 18: capacitance note 2 applies to the entire table; notes appear on page 54 parameter ? tsop ?tg? package symbol min max units notes input capacitance: clk c i 12.53.5pf29 input capacitance: all other input-only pins c i 22.53.8pf30 input/output capacitance: dqs c io 4.0 6.0 pf 31 parameter ? fbga ?fb? and ?fg? package input capacitance: clk c i 11.53.5pf34 input capacitance: all other input-only pins c i 21.53.8pf35 input/output capacitance: dqs c io 3.0 6.0 pf 36
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 51 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram electrical specifications notes: 1. auto precharge mode only . the precharge timing budget ( t rp) begins 6ns for -6a after the first clock delay, after the last write is exec uted. may not exceed lim it set for precharge mode. table 19: electrical characteristics and reco mmended ac operating conditions (-6a) notes 5, 6, 8, 9, 11, 31 apply to th e entire table; notes appear on page 54 parameter symbol -6a units notes min max access time from clk (positive edge) cl = 3 t ac(3) ?5.4ns27 address hold time t ah 0.8 ? ns address setup time t as 1.5 ? ns clk high-level width t ch 2.5 ? ns clk low-level width t cl 2.5 ? ns clock cycle time cl = 3 t ck(3) 6?ns23 cke hold time t ckh 0.8 ? ns cke setup time t cks 1.5 ? ns cs#, ras#, cas#, we#, dqm hold time t cmh 0.8 ? ns cs#, ras#, cas#, we#, dqm setup time t cms 1.5 1.5 ns data-in hold time t dh 0.8 ? ns data-in setup time t ds 1.5 ? ns data-out high-impedance time cl = 3 t hz(3) ?5.4ns10 data-out low-impedance time t lz 1?ns data-out hold time (load) t oh 3?ns data-out hold time (no load) t ohn 1.8 ? ns 28 active to precharge command t ras 42 120,000 ns active to active command period t rc 60 ? ns active to read or write delay t rcd 18 ? ns refresh period t ref ?64ms auto refresh period t rfc 60 ? ns precharge command period t rp 18 ? ns active bank a to active bank b command t rrd 12 ? ns 7 transition time t t 0.3 1.2 ns write recovery time 1 t wr 1 clk + 6ns ? ns 12 ? ns 25 exit self refresh to active command t xsr 67 ? ns 20
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 52 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram electrical specifications table 20: electrical characteristics and recomm ended ac operating conditions (-7e, -75) notes 5, 6, 8, 9, 11 apply to the entire table; note s appear on page 54 parameter symbol -7e -75 units notes min max min max access time from clk (positive edge) cl = 3 t ac(3) ? 5.4 ? 5.4 ns 27 cl = 2 t ac(2) ? 5.4 ? 6 ns address hold time t ah 0.8 ? 0.8 ? ns address setup time t as 1.5 ? 1.5 ? ns clk high-level width t ch 2.5 ? 2.5 ? ns clk low-level width t cl 2.5 ? 2.5 ? ns clock cycle time cl = 3 t ck(3) 7 ? 7.5 ? ns 23 cl = 2 t ck(2) 7.5 ? 10 ? ns 23 cke hold time t ckh 0.8 ? 0.8 ? ns cke setup time t cks 1.5 ? 1.5 ? ns 37 cs#, ras#, cas#, we#, dqm hold time t cmh 0.8 ? 0.8 ? ns cs#, ras#, cas#, we#, dqm setup time t cms 1.5 ? 1.5 ? ns data-in hold time t dh 0.8 ? 0.8 ? ns data-in setup time t ds 1.5 ? 1.5 ? ns data-out high-z time cl = 3 t hz(3) ? 5.4 ? 5.4 ns 10 cl = 2 t hz(2) ? 5.4 ? 6 ns 10 data-out low-z time t lz 1 ? 1 ? ns data-out hold time (load) t oh 3 ? 3 ? ns data-out hold time (no load) t ohn 1.8 ? 1.8 ? ns 28 active-to-precharge command t ras 37 120,000 44 120,000 ns active-to-active command period t rc 60 ? 66 ? ns active-to-read or write delay t rcd 15 ? 20 ? ns refresh period (8,192 rows) t ref ? 64 64 ms auto refresh period t rfc 66 ? 66 ? ns precharge command period t rp 15 ? 20 ? ns active bank a to active bank b command t rrd 14 ? 15 ? ns transition time t t 0.3 1.2 0.3 1.2 ns 7 write recovery time t wr 1 clk + 7ns ? 1 clk + 7.5ns ? ns 24 ?? 14 ? 15 ? ns 25 exit self refresh to active command t xsr 67 ? 75 ? ns 20
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 53 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram electrical specifications notes: 1. note 21 on page 54 does not apply for this speed grade and sh ould read ?based on t ck = 6ns.? table 21: ac functional characteristics (-6a) notes 5, 6, 7, 8, 9, 11 apply to the entire table; notes appear on page 54 parameter symbol -6a units notes read/write command to read/write command t ccd 1 t ck 17 cke to clock disable or power-down entry mode t cked 1 t ck 14 cke to clock enable or power-down exit setup mode t ped 1 t ck 14 dqm to input data delay t dqd 0 t ck 17 dqm to data mask during writes t dqm 0 t ck 17 dqm to data high-impedance during reads t dqz 2 t ck 17 write command to input data delay t dwd 0 t ck 17 data-in to active command t dal 4 t ck 15, 21 1 data-in to precharge command t dpl 2 t ck 16, 21 last data-in to burst stop command t bdl 1 t ck 17 last data-in to ne w read/write command t cdl 1 t ck 17 last data-in to precharge command t rdl 2 t ck 16, 21 load mode register command to active or refresh command t mrd 2 t ck 26 data-out to high-impedance from precharge command cl = 3 t roh(3) 3 t ck 17 table 22: ac functional characteristics (-7e, -75) notes 5, 6, 7, 8, 9, 11 apply to the entire table; notes appear on page 54 parameter symbol -7e -75 units notes read/write command to read/write command t ccd 1 1 t ck 17 cke to clock disable or power-down entry mode t cked 1 1 t ck 14 cke to clock enable or power-down exit setup mode t ped 1 1 t ck 14 dqm to input data delay t dqd 0 0 t ck 17 dqm to data mask during writes t dqm 0 0 t ck 17 dqm to data high-z during reads t dqz 2 2 t ck 17 write command to input data delay t dwd 0 0 t ck 17 data-in to active command t dal 4 5 t ck 15, 21 data-in to precharge command t dpl 2 2 t ck 16, 21 last data-in to burst stop command t bdl 1 1 t ck 17 last data-in to ne w read/write command t cdl 1 1 t ck 17 last data-in to precharge command t rdl 2 2 t ck 16, 21 load mode register command to active or refresh command t mrd 2 2 t ck 26 data-out to high-z from precharge command cl = 3 t roh(3) 3 3 t ck 17 cl = 2 t roh(2) 2 2 t ck 17
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 54 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram notes notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v dd , v dd q = +3.3v; f = 1 mhz, t a = 25c; pin under test biased at 1.4v. 3. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured; (0c t a +70c for commer- cial) and (?40c t a +85c for it). 6. an initial pause of 100s is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. (v dd and v dd q must be pow- ered up simultaneously. v ss and v ss q must be at same potential.) the two auto refresh command wake-ups should be repeated any time the t ref refresh require- ment is exceeded. 7. ac characteristics assume t t = 1ns. 8. in addition to meeting the transition rate specification, the cl ock and cke must tran- sit between v ih and v il (or between v il and v ih ) in a monotonic manner. 9. outputs measured at 1.5 v with equivalent load: 10. t hz defines the time at which the output achi eves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 11. ac operating and i dd test conditions have v il = 0v and v ih = 3.0v using a measure- ment reference level of 1.5v. if the input tran sition time is longer than 1ns, then the timing is measured from v il (max) and v ih (min) and no longer from the 1.5v mid- point. clk should always be 1.5v referenced to crossover. refer to micron technical note tn-48-09. 12. other input signals are allowed to transiti on no more than once every two clocks and are otherwise at valid v ih or v il levels. 13. i dd specifications are tested after th e device is properly initialized. 14. timing actually specified by t cks; clock(s) specified as a reference only at minimum cycle rate. 15. timing actually specified by t wr plus t rp; clock(s) specified as a reference only at minimum cycle rate. 16. timing actually specified by t wr. 17. required clocks are specified by jedec functionality and are not dependent on any timing parameter. 18. the i dd current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 19. address transitions average on e transition every two clocks. 20. clk must be toggled a minimum of two times during this period. 21. based on t ck = 7.5ns for -75 and -7e. q 50pf
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 55 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram notes 22. v ih overshoot: v ih (max) = v dd q + 2v for a pulse width 3ns, and the pulse width cannot be greater than one-third of the cycle rate. v il undershoot: v il (min) = ?2v for a pulse width 3ns. 23. the clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for th e clock pin) during access or precharge states (read, write, including t wr, and precharge commands). cke may be used to reduce the data rate. 24. auto precharge mode only. the precharge timing budget ( t rp) begins 7ns for -7e and 7.5ns for -75 after the first clock dela y, after the last write is executed. 25. precharge mode only. 26. jedec and pc100 specify three clocks. 27. t ac for -75/-7e at cl = 3 with no load is 4.6ns and is guaranteed by design. 28. parameter guaranteed by design. 29. pc100 specifies a maximum of 4pf. 30. pc100 specifies a maximum of 5pf. 31. pc100 specifies a maximum of 6.5pf. 32. for -75, cl = 3 and t ck = 7.5ns; for -7e, cl = 2 and t ck = 7.5ns. 33. cke is high during refresh command period t rfc (min) else cke is low. the i dd 6 limit is actually a nominal value and does not result in a fail value. 34. pc133 specifies a minimum of 2.5pf. 35. pc133 specifies a minimum of 2.5pf. 36. pc133 specifies a minimum of 3.0pf. 37. for operating frequencies 45 mhz, t cks = 3.0ns.
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 56 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram timing diagrams timing diagrams figure 36: initialize and load mode register notes: 1. the mode register may be loaded pr ior to the auto refresh cycles if desired. 2. if cs is high at clock high time, all commands applied are nop. 3. jedec and pc100 specify three clocks. 4. outputs are guaranteed high -z after command is issued. 5. a12 should be a low at t p + 1. t ch t cl t ck cke ck command dq ba0, ba1 bank t rfc t mrd t rfc auto refresh auto refresh program mode register 1, 3, 4 t cmh t cms precharge all banks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rp ( ) ( ) ( ) ( ) t cks power-up: v dd and clk stable t = 100s min precharge nop auto refresh nop load mode register active nop nop nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) auto refresh all banks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) high-z t ckh ( ) ( ) ( ) ( ) dqm/ dqml, dqmu ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop ( ) ( ) ( ) ( ) a0?a9, a11, a12 row t ah 5 t as code ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) a10 row t ah t as code ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) all banks single bank ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) don?t care undefined t0 t1 tn + 1 to + 1 tp + 1 tp + 2 tp + 3
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 57 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram timing diagrams figure 37: power-down mode notes: 1. violating refresh requirements during power-down may result in a loss of data. t ch t cl t ck two clock cycles cke clk dq all banks idle, enter power-down mode precharge all active banks input buffers gated off while in power-down mode exit power-down mode ( ) ( ) don?t care undefined t cks t cks command t cmh t cms precharge nop nop active nop ( ) ( ) ( ) ( ) all banks idle ba0, ba1 bank bank(s) ( ) ( ) ( ) ( ) high-z t ah t as t ckh t cks dqm/ dqml, dqmu ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) a0?a9, a11, a12 row ( ) ( ) ( ) ( ) all banks single bank a10 row ( ) ( ) ( ) ( ) t0 t1 t2 tn + 1 tn + 2 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 58 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram timing diagrams figure 38: clock suspend mode notes: 1. for this example, bl = 2, cl = 3, and auto precharge is disabled. 2. x16: a9, a11 and a12 = ?don?t care? x8: a11 and a12 = ?don?t care? x4: a12 = ?don?t care? t ch t cl t ck t ac t lz dqm/ dqml, dqmu clk a0?a9, a11, a12 dq ba0, ba1 a10 t oh d out m t ah t as t ah t as t ah t as bank t dh d in e t ac t hz d out m + 1 command t cmh t cms nop nop nop nop nop read write don?t care undefined cke t cks t ckh bank column m t ds d in + 1 nop t ckh t cks t cmh t cms 2 column e 2 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 59 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram timing diagrams figure 39: auto refresh mode notes: 1. t rfc must not be interrupted by any exec utable command; comm and inhibit or nop must be applied on each positive edge during t rfc. t ch t cl t ck cke clk dq t rfc rfc ( ) ( ) ( ) ( ) ( ) ( ) t rp ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) command t cmh t cms nop nop ( ) ( ) ( ) ( ) bank active auto refresh ( ) ( ) ( ) ( ) nop nop precharge precharge all active banks auto refresh t high-z ba0, ba1 bank(s) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t ah t as t ckh t cks ( ) ( ) nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dqm/ dqml, dqmu a0?a9, a11, a12 row ( ) ( ) ( ) ( ) all banks single bank a10 row ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) don?t care t0 t1 t2 tn + 1 to + 1
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 60 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram timing diagrams figure 40: self refresh mode notes: 1. no maximum time limit for self refresh. t ras (max) applies to non-self refresh mode. 2. t xsr requires minimum of two clocks regardless of frequency or timing. 3. as a general rule, any time self refresh is ex ited, the dram may not reenter the self refresh mode until all rows have been refreshed by the auto refresh command at the distributed refresh rate, t ref, or faster. however, the fo llowing exceptions are allowed: 3a. the dram has been in self refresh mode for a minimum of 64 ms prior to exiting. 3b. t xsr is not violated. 3c. at least two auto refresh commands are pr eformed during each 7.81s interval while the dram remains out of the self refresh mode. t ch t cl t ck t rp cke clk dq enter self refresh mode precharge all active banks t2 xsr clk stable prior to exiting self refresh mode exit self refresh mode (restart refresh time base) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) don?t care command t cmh t cms auto refresh precharge nop nop or command inhibit ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ba0, ba1 bank(s) ( ) ( ) ( ) ( ) high-z t cks ah as auto refresh t ras(min) 1 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t ckh t cks dqm/ dqml, dqmu ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t t a0?a9, a11,a12 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) all banks single bank a10 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 t2 tn + 1 to + 1 to + 2 ( ) ( ) ( ) ( )
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 61 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram timing diagrams figure 41: read ? without auto precharge notes: 1. for this example, bl = 4, cl = 2, and the read burst is followed by a ?manual? precharge. 2. x16: a9, a11, and a12 = ?don?t care? x8: a11 and a12 = ?don?t care? x4: a12 = ?don?t care? all banks t ch t cl t ck t ac t lz t rp t ras t rcd cas latency t rc dqm/ dqml, dqmu cke clk a0?a9, a11, a12 dq ba0, ba1 a10 t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row bank bank bank row row bank t hz t oh d out m + 3 t ac t oh t ac t oh t ac d out m + 2 d out m + 1 command t cmh t cms precharge nop nop nop active nop read nop active disable auto precharge single bank don?t care undefined t ckh t cks column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 62 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram timing diagrams figure 42: read ? with auto precharge notes: 1. for this example, bl = 4 and cl = 2. 2. x16: a9, a11, and a12 = ?don?t care? x8: a11 and a12 = ?don?t care? enable auto precharge t ch t cl t ck t ac t lz t rp t ras t rcd cas latency t rc dqm/ dqml, dqmu cke clk a0?a9, a11, a12 dq ba0, ba1 a10 t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row bank bank row row bank don?t care undefined t hz t oh d out m + 3 t ac t oh t ac t oh t ac d out m + 2 d out m + 1 command t cmh t cms nop nop nop active nop read nop active nop t ckh t cks column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 63 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram timing diagrams figure 43: single read ? without auto precharge notes: 1. for this example, bl = 1, cl = 2, and the read burst is followed by a ?manual? precharge. 2. precharge command not allowed (would violate t ras). 3. x16: a9, a11, and a12 = ?don?t care? x8: a11 and a12 = ?don?t care? x4: a12 = ?don?t care? all banks t ch t cl t ck t ac t lz t rp t ras t rcd cas latency t rc t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row bank bank(s) bank row row bank t hz t cmh t cms nop nop nop precharge active nop read active nop disable auto precharge single banks don?t care undefined column m 3 t ckh t cks t0 t1 t2 t3 t4 t5 t6 t7 t8 dqm/ dqml, dqmu cke clk a0?a9, a11,a12 dq ba0, ba1 a10 command 2 2
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 64 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram timing diagrams figure 44: single read ? with auto precharge notes: 1. for this example, bl = 1 and cl = 2. 2. precharge command not allowed (would violate t ras). 3. x16: a9, a11, and a12 = ?don?t care? x8: a11 and a12 = ?don?t care? x4: a12 = ?don?t care? enable auto precharge t ch t cl t ck t rp t ras t rcd cas latency t rc dqm/ dqml, dqmu cke clk a0?a9, a11 dq ba0, ba1 a10 t cmh t cms t ah t as t ah t as t ah t as row row bank bank row row bank don?t care undefined t hz t oh d out m t ac command t cmh t cms nop 2 read active nop nop 2 active nop t ckh t cks column m 3 t0 t1 t2 t4 t3 t5 t6 t7 t8 nop nop
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 65 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram timing diagrams figure 45: alternating bank read accesses notes: 1. for this example, bl = 4 and cl = 2. 2. x16: a9, a11, and a12 = ?don?t care? x8: a11 and a12 = ?don?t care? x4: a12 = ?don?t care? enable auto precharge t ch t cl t ck t ac t lz dqm/ dqml, dqmu clk a0-a9, a11, a12 dq ba0, ba1 a10 t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row row row don?t care undefined t oh d out m + 3 t ac t oh t ac t oh t ac d out m + 2 d out m + 1 command t cmh t cms nop nop active nop read nop active t oh d out b t ac t ac read enable auto precharge row active row bank 0 bank 0 bank 3 bank 3 bank 0 cke t ckh t cks column m 2 column b 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 t rp - bank 0 t ras - bank 0 t rcd - bank 0 t rcd - bank 0 cas latency - bank 0 t rcd - bank 3 cas latency - bank 3 t t rc - bank 0 rrd
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 66 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram timing diagrams figure 46: read ? full-page burst notes: 1. for this example, cl = 2. 2. x16: a9, a11, and a12 = ?don?t care? x8: a11 and a12 = ?don?t care? x4: a12 = ?don?t care? 3. page left open; no t rp. t ch t cl t ck t ac t lz t rcd cas latency dqm/ dqml, dqmu cke clk a0?a9, a11, a12 dq ba0, ba1 a10 t oh d out m t cmh t cms t ah t as t ah t as t ac t oh d out m +1 row row t hz t ac t oh d out m +1 t ac t oh d out m +2 t ac t oh d out m -1 t ac t oh dout m full-page burst does not self-terminate. can use burst terminate command. ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) full page completed 512 (x16) locations within same row 1,024 (x8) locations within same row 2,048 (x4) locations within same row don?t care undefined command t cmh t cms nop nop nop active nop read nop burst term nop nop ( ) ( ) ( ) ( ) nop ( ) ( ) ( ) ( ) t ah t as bank ( ) ( ) ( ) ( ) bank t ckh t cks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) column m 2 3 t0 t1 t2 t4 t3 t5 t6 tn + 1 tn + 2 tn + 3 tn + 4
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 67 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram timing diagrams figure 47: read ? dqm operation notes: 1. for this example, bl = 4 and cl = 2. 2. x16: a9, a11, and a12 = ?don?t care? x8: a11 and a12 = ?don?t care? x4: a12 = ?don?t care? t ch t cl t ck t rcd cas latency dqm/ dqml, dqmu cke clk a0?a9, a11, a12 dq ba0, ba1 a10 t cms row bank row bank don?t care undefined t ac lz d out m t oh d out m + 3 d out m + 2 t t hz lz t t cmh command nop nop nop active nop read nop nop nop t hz t ac t oh t ac t oh t ah t as t cms t cmh t ah t as t ah t as t ckh t cks enable auto precharge disable auto precharge column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 68 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram timing diagrams figure 48: write ? without auto precharge notes: 1. for this example, bl = 4, and the wri te burst is followed by a ?manual? precharge. 2. 14ns to 15ns is required between and the precharge command, regardless of frequency. 3. x16: a9, a11, and a12 = ?don?t care? x8: a11 and a12 = ?don?t care? x4: a12 = ?don?t care? disable auto precharge t ch t cl t ck t rp t ras t rcd t rc dqm/ dqml, dqmu cke clk a0?a9, a11, a12 dq ba0, ba1 a10 t cmh t cms t ah t as row bank bank row bank t don?t care d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 command t cmh t cms nop nop nop active nop write precharge t ah t as t ah t as t dh t ds t dh t ds t dh t ds single bank t ckh t cks column m 2 3 t0 t1 t2 t4 t3 t5 t6 t7 t8 t9 row bank row active nop wr nop all banks
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 69 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram timing diagrams figure 49: write ? with auto precharge notes: 1. for this example, bl = 4. 2. x16: a9, a11, and a12 = ?don?t care? x8: a11 and a12 = ?don?t care? x4: a12 = ?don?t care? enable auto precharge t ch t cl t ck t rp t ras t rcd t rc dqm/ dqml, dqmu cke clk a0?a9, a11, a12 dq ba0, ba1 a10 t cmh t cms t ah t as row row bank bank row row bank t wr don?t care d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 command t cmh t cms nop nop nop active nop write nop active t ah t as t ah t as t dh t ds t dh t ds t dh t ds t ckh t cks nop nop column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 t9
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 70 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram timing diagrams figure 50: single write ? without auto precharge notes: 1. for this example, bl = 1, and the wri te burst is followed by a ?manual? precharge. 2. 14ns to 15ns is required between and the precharge comma nd, regardless of fre- quency. with a single write, t wr has been increased to meet minimum t ras requirement. 3. x16: a8, a9, and a11 = ?don?t care? x8: a9 and a11 = ?don?t care? x4: a11 = ?don?t care? 4. precharge command not allowed (would violate t ras). disable auto precharge all banks t ch t cl t ck t rp t ras t rcd t rc dqm/ dqml, dqmu cke clk a0?a9, a11 dq ba0, ba1 a10 t cmh t cms t ah t as row bank bank bank row row bank t wr d in m t dh t ds command t cmh t cms nop 2 nop 2 precharge active nop write active nop nop t ah t as t ah t as single bank t ckh t cks column m 3 4 t0 t1 t2 t4 t3 t5 t6 t7 t8 don?t care
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 71 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram timing diagrams figure 51: single write ? with auto precharge notes: 1. for this example, bl = 1. 2. requires one clock plus time (7ns to 7.5ns) with auto prec harge or 14ns to 15ns with pre- charge. 3. x16: a9, a11, and a12 = ?don?t care? x8: a11 and a12 = ?don?t care? x4: a12 = ?don?t care? 4. write command not allowed (would violate t ras). enable auto precharge t ch t cl t ck t rp t ras t rcd t rc dqm/ dqml, dqmu cke ck a0?a9, a11, a12 dq ba0, ba1 a10 t cmh t cms t ah t as row row bank bank row row bank t wr 4 d in m command t cmh t cms nop 2 nop 2 nop active nop 2 write nop active t ah t as t ah t as t dh t ds t ckh t cks nop nop column m 3 t0 t1 t2 t4 t3 t5 t6 t7 t8 t9 don?t care
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 72 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram timing diagrams figure 52: alternating bank write accesses notes: 1. for this example, bl = 4. 2. requires one clock plus time (7ns or 7.5ns) with auto prec harge or 14ns to 15ns with pre- charge. 3. x16: a9, a11, and a12 = ?don?t care? x8: a11 and a12 = ?don?t care? x4: a12 = ?don?t care? t ch t cl t ck clk dq don?t care d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 command t cmh t cms nop nop active nop write nop nop active t dh t ds t dh t ds t dh t ds active write d in b t dh t ds d in b + 1 d in b + 3 t dh t ds t dh t ds enable auto precharge dqm/ dqml, dqmu a0?a9, a11, a12 ba0, ba1 a10 t cmh t cms t ah t as t ah t as t ah t as row row row row enable auto precharge row row bank 0 bank 0 bank 1 bank 0 bank 1 cke t ckh t cks d in b + 2 t dh t ds column b 3 column m 3 t rp - bank 0 t ras - bank 0 t rcd - bank 0 t t rcd - bank 0 t wr - bank 0 wr - bank 1 t rcd - bank 1 t t rc - bank 0 rrd t0 t1 t2 t3 t4 t5 t6 t7 t8 t9
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 73 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram timing diagrams figure 53: write ? full-page burst notes: 1. x16: a9, a11, and a12 = ?don?t care? x8: a11 and a12 = ?don?t care? x4: a12 = ?don?t care? 2. t wr must be satisfied pr ior to prechar ge command. 3. page left open; no t rp. t ch t cl t ck t rcd dqm/ dqml, dqmu cke clk a0?a9, a11, a12 ba0, ba1 a10 t cms t ah t as t ah t as row row full-page burst does not self-terminate. can use burst terminate command to stop. 2, 3 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) full page completed don?t care command t cmh t cms nop nop nop active nop write burst term nop nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dq d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 t dh t ds t dh t ds t dh t ds d in m - 1 t dh t ds t ah t as bank ( ) ( ) ( ) ( ) bank t cmh t ckh t cks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) 512 (x16) locations within same row 1,024 (x8) locations within same row 2,048 (x4) locations within same row column m 1 t0 t1 t2 t3 t4 t5 tn + 1 tn + 2 tn + 3
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 74 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram timing diagrams figure 54: write ? dqm operation notes: 1. for this example, bl = 4. 2. x16: a9, a11, and a12 = ?don?t care? x8: a11 and a12 = ?don?t care? x4: a12 = ?don?t care? t ch t cl t ck t rcd dqm/ dqml, dqmu cke clk a0?a9, a11, a12 dq ba0, ba1 a10 t cms t ah t as row bank row bank enable auto precharge d in m + 3 t dh t ds d in m d in m + 2 t cmh command nop nop nop active nop write nop nop don?t care t cms t cmh t dh t ds t dh t ds t ah t as t ah t as disable auto precharge t ckh t cks column m 2 t0 t1 t2 t3 t4 t5 t6 t7
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 75 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram package dimensions package dimensions figure 55: 54-pin plastic tsop (400 mil) notes: 1. all dimensions in millimeters. 2. package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. ?2x? means the notch is present in tw o locations (both ends of the device). see detail a 0.10 +0.10 -0.05 0.15 +0.03 -0.02 2x r 1.00 2x r 0.75 0.80 typ (for reference only) 2x 0.71 0.50 0.10 pin #1 id detail a 22.22 .08 10.16 0.08 11.76 0.20 0.375 0.075 typ 1.2 max 0.25 0.80 2x 0.10 2.80 gage plane plated lead finish: 90% sn, 10% pb or 100%sn plastic package material: epoxy novolac package width and length do not include mold protrusion. allowable protrusion is 0.25 per side. 0.10
pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 76 ?1999 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 sdram package dimensions figure 56: 60-ball fbga ?fb? package, 8mm x 16mm (x4, x8) notes: 1. all dimensions in millimeters. 2. recommended pad size for pcb is 0.33mm 0.025mm. 3. topside part marking decode can be foun d at: www.micron.com/su pport/designsupport/ tools/fbga/decoder. ball #1 id substrate: plastic laminate encapsulation material: epoxy novolac solder ball material: 62% sn, 36% pb, 2% ag or 96.5% sn. 3% ag, 0.5% cu seating plane 0.850 0.05 0.10 a a 0.80 typ 16.00 0.10 11.20 1.20 max 5.60 8.00 0.05 ball #1 id ball a1 ball a8 0.80 typ 4.00 0.05 2.80 2.40 0.05 ctr 8.00 0.10 5.60 60x ? 0.45 dimensions apply to solder balls post reflow. pre- reflow diameter is 0.42 on a 0.33 nsmd ball pad. c l
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo ar e trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified ov er the complete power supply and temperature range set forth herein. although considered fina l, these specifications are subject to ch ange, as further produ ct development and data characterization sometimes occur. 256mb: x4, x8, x16 sdram package dimensions pdf: 09005aef8091e6d1/source: 09005aef8091e6a8 micron technology, inc., reserves the right to change products or specifications without notice. 256msdram_2.fm - rev. l 10/07 en 77 ?1999 micron technology, inc. all rights reserved. figure 57: 54-ball vfbga ?fg? package, 8mm x 14mm (x16) notes: 1. all dimensions in millimeters. 2. recommended pad size for pcb is 0.4mm 0.065mm. 3. topside part marking decode can be found at: http://www.micron.com/decoder . ball a1 id 1.00 max mold compound: epoxy novolac substrate material: plastic laminate solder ball material: 62% sn, 36% pb, 2% ag or 96.5% sn, 3%ag, 0.5% cu solder mask defined ball pads: ? 0.40 14.00 0.10 ball a1 ball a9 ball a1 id 0.80 typ 0.80 typ 7.00 0.05 8.00 0.10 4.00 0.05 3.20 0.05 3.20 0.05 0.65 0.05 seating plane c 6.40 6.40 0.10 c 54x ?0.45 solder ball diameter refers to post reflow condition. the pre- reflow diameter is ?0.42 c l c l

▲Up To Search▲

Price & Availability of 48LC16M16A2

	To Download 48LC16M16A2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .